1. Field of the Invention
The present invention relates to a latch control circuit, and more particularly, to a digital latch control circuit applied for over-voltage protection.
2. Description of the Prior Art
Generally speaking, a power converter utilizes an over-voltage protection scheme to prevent an internal high voltage signal from exceeding a particular voltage level. Please refer to FIG. 1, which is a schematic diagram of a conventional power converter 100. The power converter 100 is a flyback converter comprising a bridge rectifier 105, a transformer TX1 having a primary-side winding LP, second-side winding LS, and an auxiliary winding Laux, a diode D1, capacitors C1 and C2, resistors R1, R2, Rp, and Rn, transistors Q1 and Q2, and a de-glitch circuit 110. Those skilled in this art should appreciate circuit design of this flyback converter, and detailed description for the circuit design of the power converter 100 is not illustrated for brevity. The above-mentioned over-voltage protection scheme applied to the power converter 100 is for detecting whether the level of the supply voltage VCC at the capacitor C2 becomes over higher, for avoiding damage to internal circuit elements within the power converter 100. If the power converter 100 does not include the resistors Rp and Rn and the transistors Q1 and Q2, the primary-side winding LP of the transformer TX1 does not transfer energy from the AC input voltage VAC to the secondary-side winding LS when detecting the supply voltage VCC becoming overly high (i.e., an abnormal condition). The auxiliary winding Laux cannot obtain the energy coming from the AC input voltage VAC, so the level of the supply voltage VCC decreases. The primary-side winding LP transfers the energy from the AC input voltage VAC to the secondary-side winding LS until the supply voltage VCC becomes equal to or lower than a voltage level at which the internal circuit elements within the power converter 100 can work normally. But, if the abnormal condition still exists, the level of the supply voltage VCC will increase and become overly high again. In other words, if an abnormal condition to the power converter 100 still exists, the level of the supply voltage VCC will repeatedly exceed the threshold and drop lower.
The power converter 100 may include resistors Rp and Rn and transistors Q1 and Q2 for solving the above-described problems. With regards to other circuit elements within the power converter 100, the resistors Rp and Rn and the transistors Q1 and Q2 are externally coupled circuit elements. When detecting that the supply voltage VCC becomes overly high, an over-voltage protection trigger signal OVPtrigger is triggered and then sent to the base terminal (i.e., node N1) of transistor Q2 to increase the voltage level at node N1 and turn on transistor Q2. Since the transistor Q2 becomes conductive, the voltage level at node N2 decreases so that transistor Q1 then also becomes conductive. In this situation, although the level of the over-voltage protection trigger signal OVPtrigger is not kept at a high logic level, the voltage level at node N1 increases since the transistor Q1 becomes conductive. As a result, the transistors Q1 and Q2 are eventually fully turned on, and the level of the supply voltage VCC becomes lower and is maintained at a lower level, which is caused by a voltage division resulting from the AC input voltage VAC passing through diodes of the bridge rectifier 105, the resistor R1, and an impedance formed by the resistors Rp and Rn being connected in parallel. Therefore, the level of the supply voltage VCC will not repeatedly become cycle overly higher and then lower.
The power converter 100, however, still has some drawbacks. The transistors Q1 and Q2 and the resistors Rp and Rn form an analog circuit, the transistors Q1 and Q2 are not conductive under normal condition, and nodes N1 and N2 are seen as high impedence points. In this situation, the impedences seen from nodes N1 and N2 are very high. If noise arises, it can easily make the transistors Q1 and Q2 become conductive so that the power converter 100 operates erroneously. In order to solve this problem, it is necessary to add a de-glitch circuit (e.g., the de-glitch circuit 110 of the power converter 100 shown in FIG. 1) at node N1. Doing so, however, increases production costs and need larger circuit area. In addition, since the de-glitch circuit 110 has to operate when the power converter 100 powers on, additional current must be provided for the de-glitch circuit 110 when the power converter 100 powers on.